1. Field of the Invention
This invention relates generally to switching power converters, and more particularly to current mode switching converters that employ a ‘skip’ mode to prevent inductor current runaway during start-up.
2. Description of the Related Art
One method of controlling a switching converter is referred to as “current mode” control, in which the inductor current is used to regulate the output voltage. To prevent the noise generated by an ‘off’ to ‘on’ transition of the converter's high side switching element from corrupting the sensing of the inductor current, such a converter typically employs a “blanking time” at the transition point, which prevents the high side switching element from being switched off due to the noise. The duration of the “blanking time” is referred to as the converter's “minimum on-time”.
However, since the high side switching element cannot be turned off during the blanking time, the inductor current will continue to increase throughout this interval. This may result in the inductor current becoming excessively high when the converter is first started up (sometimes referred to as ‘soft-start’) and the regulation loop is not yet in full operation, especially when the switching frequency is high.
One conventional solution for this problem is to introduce a pulsed-frequency mode (PFM) of operation during start-up, which under certain conditions causes a ‘skip mode’ to be triggered during which the operation of the switching elements is temporarily suspended. An example of such a converter is shown in FIG. 1. High and low side switching elements 10 and 12 are driven by pulse-width modulated (PWM) drive signals received from a gate driver 14, which is driven with a PWM signal 16 provided by an SR latch 18 to regulate the converter's output voltage Vout. An oscillator 20 provides a clock signal Clk_shot which is applied to the SET input of latch 18 such that, in normal operation, the latch is set and high side switching element 10 is turned on each time the Clk_shot signal pulses.
An error amplifier 22 produces an output VCOMP which varies with the difference between a voltage VFB that varies with Vout and a reference voltage VREF. VCOMP is summed with a slope compensation signal VRAMP to provide a voltage VC. Voltage VC and a signal IDETECT—PEAK, which varies with the current conducted by high side switching element 10, are provided to a PWM comparator 24, the output 26 of which is used to reset latch 18 in normal operation.
To prevent inductor current runaway during start-up, voltage VC is provided to a pulsed-frequency modulated (PFM) comparator 28, which also receives a predetermined PFM threshold voltage VPFM. When VC is less than VPFM, the output ‘skip’ of comparator 28 goes high. An OR gate 32 receives the output 26 from comparator 24 and output ‘skip’ from comparator 28 at respective inputs, and produces an output 34 which is applied to the RESET input of SR latch 18.
The operation of the converter of FIG. 1 is illustrated with the timing diagram shown in FIG. 2. When VC is less than VPFM, this indicates that the control loop is calling for very little inductor current (IL), which is an indication that IL is too high. During these periods, the ‘skip’ output and thus the RESET input of latch 18 are high, and the converter operates in skip mode; this prevents the latch from being set and thus no new PWM pulses are delivered to switching elements 10 and 12. However, when VC is greater than VPFM, this indicates that the inductor current is at an acceptable level, and thus PWM pulses which regulate Vout are provided to switching elements 10 and 12.
This approach has a drawback, however, due to the fact that there is a phase lag in which VCOMP and VC lag behind inductor current IL; this is due to the effects of the converter's output capacitor Cout and the compensation components 35 typically found in such converters. Thus, at start-up when Vout is close to zero, several minimum on-time pulses 34 can be generated before skip mode can be triggered. This may result in an unacceptably high inductor current 36, especially when the switching frequency is high. Moreover, transitions between skip mode and the normal PWM mode can cause output voltage Vout to dip and recover as it increases from zero, resulting in a large output ripple.